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Architetture RISC
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Bibliografia

  1. E. Basart, "RISC design streamlines high-power CPUs," Computer Design, July 1, 1985, pp. 119-122.
  2. R. Bernhard, "More hardware means less software," IEEE Spectrum, Dec. 1981.
  3. R. Bernhard, "RISCs -- Reduced instruction set computers -- make leap," Syst. Software, Dec. 1984, pp. 81-84.
  4. J. Birnbaum, W. Worley, "Beyond RISC: High-precision architecture," in Proc. Compcon Spring 86 (Mar. 1986), pp. 40-47.
  5. J. Browne, "Understanding execution behavior of software systems," Computer, vol. 17, July 1984, pp. 83-87.
  6. C. Bruno, S. Brady, "The RISC factor," Datamation, June 1, 1986, pp. y-DD.
  7. G. Chaitin, "Register allocation and spilling via graph coloring," in Proc. SIGPLAN Symp. on Compiler Construction (June 1982), pp. 98-105.
  8. F. Chow et al., "Engineering a RISC compiler system," in Proc. Compcon Spring 86 (Mar. 1986), pp. 132-137.
  9. R.P. Colwell et al., "Instruction sets and beyond: Computers, complexity, and controversy," Computer, vol. 18, Sept. 1985, pp. 8-19.
  10. R. Colwell et al., "More controversy about 'Computers, complexity, and controversy,'" Computer, Dec. 1985, p. 93.
  11. D. Coutant et al., "Compilers for the new generation of Hewlett-Packard computers," in Proc. Compcon Spring 86 (Mar. 1986), pp. 182-195.
  12. D. Fitzpatrick et al., "A RISCy approach to VLSI," VLSI Des., 4th Quarter, 1981, pp. 14-20.
  13. S. Gannes, "Back-to-basics computers with sports-car speed," Fortune, Sept. 30, 1985, pp. 98-101.
  14. J. Heath, "Re-evaluation of RISC I," Comput. Arch. News, Mar. 1984.
  15. J. Hennessy et al., "Hardware/software tradeoffs for increased performance," in Proc. Symp. on Architectural Support for Programming Languages and Operating Systems, Mar. 1982, pp. 2-11.
  16. J.L. Hennessy, "VLSI processor architecture," IEEE Trans. Comput., vol. C-33, Dec. 1984, pp. 1221-1246.
  17. J. Hennessy, T. Gross, "Postpass code optimization of pipeline constraints," ACM Trans. Programming Languages Syst., July 1983.
  18. T. Huck, "Comparative analysis of computer architectures," Stanford Univ. Tech. Rep. 83-243, May 1983.
  19. M. Katevenis, "Reduced instruction set architectures for VLSI," Ph.D. Dissertation, Computer Sci. Dep., Univ. of California at Berkeley, Oct. 1983. Reprinted by MIT Press, Cambridge, MA, 1985.
  20. D. Knuth, "An empirical study of FORTRAN programs," Software Practice Exper., vol. 1, 1971, pp. 105-133.
  21. A. Lunde, "Empirical evaluation of some features of instruction set processor architectures," Commun. ACM, Mar. 1972, pp. 143-153.
  22. M. Miller, "Simplicity is focus in efforts to increase computer power," The Wall Street J., Aug. 23, 1985, p. 17.
  23. N. Mokhoff, "New RISC machines appear as hybrids with both RISC and CISC features," Computer Design, Apr. 1, 1986, pp. 22-25.
  24. J. Moussouris et al., "A CMOS RISC processor with integrated system functions," in Proc. Compcon Spring 86 (Mar. 1986), pp. 126-131.
  25. G. Myers, "The evaluation of expressions in a storage-to- storage architecture," Computer Arch. News, June 1978.
  26. L. Neff, "Clipper microprocessor architecture overview," in Proc. Compcon Spring 86 (Mar. 1986), pp. 191-195.
  27. S. Ohr, "RISC machines," Electronic Design, Jan. 10, 1985, pp. 175-190.
  28. D. Patterson, "Reduced instruction set computers," Commun. ACM, Jan. 1985, pp. 8-21.
  29. D. Patterson, "RISC watch," Comput. Arch. News, Mar. 1984.
  30. D. Patterson, C. Sequin, "A VLSI RISC," Computer, Sept. 1982, pp. 8-22.
  31. D. Patterson, J. Hennessy, "Comments, with reply on 'Computers, complexity, and controversy' by R.P. Colwell et al.," Computer, vol. 18, Nov. 1985, pp. 142-143.
  32. D. Patterson, R. Piepho, "Assessing RISCs in high-level language support," IEEE Micro, vol. 2, Nov. 1982, pp. 9-18.
  33. G. Radin, "The 801 minicomputer," IBM J. Res. Dev., May 1983, pp. 237-246.
  34. R. Ragan-Kelley, R. Clark, "Applying RISC theory to a large computer," Computer Design, Nov. 1983, pp. 191-198.
  35. C. Rowen et al., "RISC VLSI design for system-level performance," VLSI Syst. Des., Mar. 1986.
  36. M. Seither, "Pyramid challenges DEC with RISC supermini," Mini-Micro Systems, Aug. 1985, pp. 33-36.
  37. O. Serlin, "MIPS, dhrystones, and other tales," Datamation, June 1, 1986, pp. 112-118.
  38. R. Sherburne, "Processor design tradeoffs in VLSI," Ph.D. Dissertation, Rep. UCB/CSD 84/173, Univ. of California at Berkeley, Apr. 1984.
  39. W. Stallings, "Reduced Instruction Set Computer architecture," Proceedings of the IEEE, vol. 76, no. 1, January 1988, pp. 38-55.
  40. W. Stallings, Computer Organization and Architecture, New York, NY: Macmillan, 1987.
  41. W. Stallings, Reduced Instruction Set Computers, Washington, DC: IEEE Computer Soc. Press, 1986.
  42. Y. Tamir, C. Sequin, "Strategies for managing the register file in RISC," IEEE Trans. Comput., vol. C-30, Nov. 1983, pp. 977- 988.
  43. A. Tanenbaum, "Implications of structured programming for machine architecture," Commun. ACM, Mar. 1978, pp. 237-246.
  44. P. Wallich, "Toward simpler, faster computers," IEEE Spectrum, vol. 22, Aug. 1985, pp. 38-45.
  45. F. Waters, Ed., IBM RT Personal Computer Technology, IBM Publ. SA23-1057, 1986.
  46. R. Weiss, "RISC processors: The new wave in computer systems," Computer Design, May 15, 1987, pp. 53-73.
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Architetture RISC
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© 1997-2003 Paolo Marincola (Rome, Italy)
e-mail: pmaNOSPAM@acm.org (eliminare i caratteri "NOSPAM" per ottenere l'indirizzo esatto)
Commenti, osservazioni e suggerimenti sono estremamente graditi.

Last revised: 2003-12-06 19:48